The present invention relates to a semiconductor memory device and, more particularly, to an electrically programmable erasable semiconductor memory device.
A conventional electrically programmable erasable flash memory will be explained with reference to FIGS. 5A and 5B. In FIG. 5B, each floating gate 603 is formed on a semiconductor substrate 601 via a gate insulating film 602. A control gate 605 is formed on the floating gate 603 via an insulating film (ONO film) 604. The insulating film 604 has a three-layered structure obtained by sandwiching a silicon nitride film between silicon oxide films.
An impurity-diffused drain 606 and source 607 are formed in the semiconductor substrate 601 on the two sides of the floating gate 603. An interlevel insulating film 610 is formed on the semiconductor substrate 601 to cover the control gate 605. A contact 609a is formed in the interlevel insulating film 610 on the drain 606.
As shown in FIG. 5A, memory cell arrays are formed in the longitudinal direction (lateral direction in FIG. 5A) of the gate to share the drains 606 and the sources 607. In a direction (longitudinal direction in FIG. 5) perpendicular to the longitudinal direction of the gate, a plurality of memory cells defined by element isolation regions 608 on the drain 606 side are formed to constitute memory cell arrays. In each memory cell, the contact 609a is formed on the drain 606. To the contrary, the source 607 side is not partitioned. The common source 607 is continuously formed for a plurality of memory cells on a memory cell array, and one contact 609b is formed for adjacent memory cell arrays.
To form the drain contact 609a, the impurity-diffused region must be wide to a certain degree. Since the source contact 609b need not be formed for each memory cell, one source contact 609b can be shared by one memory cell array, as shown in FIG. 5A. With this arrangement, the interval between the common sources of memory cell arrays can be decreased, thereby reducing the cell size.
The operation of the conventional flash memory will be described. A state of "1" and "0" of the memory cell is set by forming a state wherein electrons enter the floating gate 603 electrically insulated from the surroundings, or a state wherein no electron enters the floating gate 603.
Electrons are injected into the floating gate 603 by the following method. A positive high voltage of 12 V is applied to the control gate 605, and a positive voltage of 6 V is applied to the drain 606. Then, hot electrons are produced near the drain of a channel formed below the gate insulating film 602. Some of the hot electrons are injected into the floating gate 603 (CHE injection).
According to another method, a positive high voltage of 16 V is applied to only the control gate 605 to inject electrons by an FN tunnel current (FN injection).
On the other hand, electrons are extracted from the floating gate 603 by the following method. A negative voltage of -9 V is applied to the control gate 605, and a positive voltage of 5 V is applied to the drain 606 to extract electrons by an FN tunnel current (drain-gate extraction).
By still another method, a positive high voltage of 11 V is applied to only the source 607 to extract electrons (source extraction).
According to still another method, a positive high voltage of 15 V is applied to only the semiconductor substrate 601 (channel) to extract electrons in the floating gate 603 (channel extraction).
To cope with a microcomputer operating at a high speed, a hybrid flash memory must perform a high-speed read, which is unimportant in the use of the conventional flash memory alone. However, a cell array in which the sources of memory cells are connected to contact each other at one portion in the above-mentioned manner is unsuitable for a high-speed read because a high source resistance is generated in a memory cell distant from the contact, and no ON current flows.
In a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in a logic circuit or the like to reduce the source resistance, e.g., a titanium silicide layer is formed on the source and drain surfaces of a semiconductor substrate in order to reduce the contact resistance in the source and drain. If the titanium silicide layer is formed on the surface of a source formation region in the above cell array, the source resistance can be reduced in even a memory cell distant from the common contact.
However, silicon heavily doped with arsenic hardly silicifies with titanium. To silicify silicon with titanium, the dose of arsenic as an impurity in silicon must be 2.times.10.sup.15 /cm.sup.2 or less.
In the flash memory, the arsenic dose in the source and drain must be 5.times.10.sup.15 /cm.sup.2 or more to increase the write/erase speed. If the arsenic dose in the diffusion layer is high, no titanium silicide layer can be formed, as described above.
The conventional flash memory cannot therefore perform high-speed read because the source contact is shared by a plurality of memory cells to reduce the cell size.